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| DS1210 DS1210 Nonvolatile Controller Chip FEATURES PIN ASSIGNMENT VCCO 1 2 3 4 8 7 6 5 VCCI VBAT2 CEO CE * Converts CMOS RAMs into nonvolatile memories * Unconditionally tolerance write protects when VCC is out of VBAT1 TOL GND * Automatically occurs switches to battery when power fail * Space saving 8-pin DIP * Consumes less than 100 nA of battery current * Tests battery condition on power up * Provides for redundant batteries * Optional 5% or 10% power fail detection * Low forward voltage drop on the VCC switch * Optional 16-pin SOIC surface mount package * Optional industrial temperature range of -40C to +85C. VCCO VBAT1 TOL GND CE CEO VBAT2 VCCI NC DS1210 8-Pin DIP (300 MIL) NC VCCO NC VBAT1 NC TOL NC GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC VCCI NC VBAT2 NC CEO NC CE DS1210S 16-Pin SOIC (300 MIL) PIN DESCRIPTION - - - - - - - - - RAM Supply + Battery 1 Power Supply Tolerance Ground Chip Enable Input Chip Enable Output + Battery 2 + Supply No Connect DESCRIPTION The DS1210 Nonvolatile Controller Chip is a CMOS circuit which solves the application problem of converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-of-tolerance condition. When such a condition is detected, chip enable is inhibited to accomplish write protection and the battery is switched on to supply the RAM with uninterrupted power. Special circuitry uses a low-leakage CMOS process which affords precise voltage detection at extremely low battery consumption. The 8-pin DIP package keeps PC board real estate requirements to a minimum. By combining the DS1210 Nonvolatile Controller Chip with a CMOS memory and batteries, nonvolatile RAM operation can be achieved. ECopyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor databooks. 011592 1/7 DS1210 OPERATION The DS1210 nonvolatile controller performs five circuit functions required to battery back up a RAM. First, a switch is provided to direct power from the battery or the incoming supply (VCCI) depending on which is greater. This switch has a voltage drop of less than 0.3V. The second function which the nonvolatile controller provides is power fail detection. The DS1210 constantly monitors the incoming supply. When the supply goes out of tolerance a precision comparator detects power fail and inhibits chip enable (CEO). The third function of write protection is accomplished by holding the CEO output signal to within 0.2 volts of the VCCI or battery supply. If CE input is low at the time power fail detection occurs, the CEO output is kept in its present state until CE is returned high. The delay of write protection until the current memory cycle is completed prevents the corruption of data. Power fail detection occurs in the range of 4.75 volts to 4.5 volts with the tolerance Pin 3 grounded . If Pin 3 in connected to VCCO, then power fail detection occurs in the range of 4.5 volts to 4.25 volts. During nominal supply conditions CEO will follow CE with a maximum propagation delay of 20ns. The fourth function the DS1210 performs is a battery status warning so that potential data loss is avoided. Each time that the circuit is powered up the battery voltage is checked with a precision comparator. If the battery voltage is less than 2.0 volts, the second memory cycle is inhibited. Battery status can, therefore, be determined by performing a read cycle after power-up to any location in memory, verifying that memory location content. A subsequent write cycle can then be executed to the same memory location altering the data. If the next read cycle fails to verify the written data, then the batteries are less than 2.0V and data is in danger of being corrupted. The fifth function of the nonvolatile controller provides for battery redundancy. In many applications, data integrity is paramount. In these applications it is often desirable to use two batteries to ensure reliability. The DS1210 controller provides an internal isolation switch which allows the connection of two batteries. During battery backup operation the battery with the highest voltage is selected for use. If one battery should fail, the other will take over the load. The switch to a redundant battery is transparent to circuit operation and to the user. A battery status warning will occur when the battery in use falls below 2.0 volts. A grounded VBAT2 pin will not activate a battery fail warning. In applications where battery redundancy is not required, a single battery should be connected to the BAT1 pin. The BAT2 battery pin must be grounded. The nonvolatile controller contains circuitry to turn off the battery back-up. This is to maintain the battery(s) at its highest capacity until the equipment is powered up and valid data is written to the SRAM. While in the freshness seal mode the CEO and VCCO will be forced to VOL. When the batteries are first attached to one or both of the VBAT pins, VCCO will not provide battery back-up until VCCI exceeds VCCTP, as set by the TOL pin, and then falls below VBAT. Figure 1 shows a typical application incorporating the DS1210 in a microprocessor-based system. Section A shows the connections necessary to write protect the RAM when VCC is less than 4.75 volts and to back up the supply with batteries. Section B shows the use of the DS1210 to halt the processor when VCC is less than 4.75 volts and to delay its restart on power- up to prevent spurious writes. SECTION A - BATTERY BACKUP Figure 1 VCCO DS1210 +5V VCCI 8 1 2 7 CE 5 4 6 3 CE VBAT2 VBAT1 VCC CMOS RAM FROM DECODER GND 011592 2/7 DS1210 BATTERY BACKUP CURRENT DRAIN EXAMPLE CONSUMPTION DS1210 IBAT RAM ICC02 Total Drain 100 nA 10 A 10.1 A SECTION B - PROCESSOR RESET +5V VCCI DS1210 VBAT1 2 8 VBAT2 TOL 7 CEO 6 3 PROCESSOR RESET CE 5 4 FROM PUSH BUTTON RESET 011592 3/7 DS1210 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Pin 3 = GND Supply Voltage Pin 3 = VCCO Supply Voltage Logic 1 Input Logic 0 Input Battery Input SYMBOL VCCI VCCI VIH VIL VBAT1, VBAT2 MIN 4.75 4.5 2.2 -0.3 2.0 TYP 5.0 5.0 MAX 5.5 5.5 VCC+0.3 +0.8 4.0 UNITS V V V V V (0C to 70C) NOTES 1 1 1 1 1,2 DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Current Supply Voltage Supply Current Input Leakage Output Leakage CEO Output @2.4V CEO Output @0.4V VCC Trip Point (TOL=GND) VCC Trip Point (TOL=VCCO) SYMBOL ICCI VCCO ICCO1 IIL ILO IOH IOL VCCTP VCCTP (0C to 70C; VCCI = 4.75V to 5.5V, PIN 3 = GND) (VCCI = 4.5 to 5.5V, PIN 3 = VCCO) MIN TYP MAX 5 VCC-0.2 80 -1.0 -1.0 -1.0 4.0 4.50 4.25 4.62 4.37 4.74 4.49 +1.0 +1.0 UNITS mA V mA A A mA mA V V 5 5 1 1 NOTES 3 1 4 (0C to 70C; VCCI = < VBAT) CEO Output VBAT1 or VBAT2 Battery Current Battery Backup Current @ Vcco = VBAT - 0.3V VOHL IBAT ICCO2 VBAT-0.2 100 50 V nA A 7 2,3 6,7 011592 4/7 DS1210 CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 5 7 UNITS pF pF (TA = 25C) NOTES AC ELECTRICAL CHARACTERISTICS PARAMETER CE Propagation Delay CE High to Power Fail SYMBOL tPD tPF 5 (0C to 70C; VCCI = 4.75V to 5.5V, PIN 3 = GND) (VCCI = 4.5 to 5.5V, PIN3 = VCCO) MIN TYP 10 MAX 20 0 UNITS ns ns NOTES 5 (0C to 70C; VCCI < 4.75V, PIN 3 = GND; VCCI < 4.5, PIN 3 = VCCO) Recovery at Power Up VCC Slew Rate Power Down VCC Slew Rate Power Down VCC Slew Rate Power Up CE Pulse Width tREC tF tFB tR tCE 2 300 10 0 1.5 80 125 ms s s s s 8 NOTES: 1. All voltages are referenced to ground. 2. Only one battery input is required. Unused battery inputs must be grounded. 3. Measured with VCCO and CEO open. 4. ICC01 is the maximum average load which the DS1210 can supply to the memories. 5. Measured with a load as shown in Figure 2. 6. ICC02 is the maximum average load current which the DS1210 can supply to the memories in the battery backup mode. 7. tCE max. must be met to ensure data integrity on power loss. 8. CEO can only sustain leakage current in the battery backup mode. 011592 5/7 DS1210 TIMING DIAGRAM: POWER UP CE VIH VBAT-0.2V VIH CEO tPD tREC 4.75V 4.5V 4.25V VCCI tR TIMING DIAGRAM: POWER DOWN tCE CE VIH VIL tPD tCE CEO VIH VIL VBAT-0.2V tPF tF VCC 4.75V 4.5V 4.25V 3V tFB 011592 6/7 DS1210 OUTPUT LOAD Figure 2 +5 VOLTS PIN 6 CEO 1.1K 680W 50pF 011592 7/7 |
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